Computation of floating mode delay in combinational circuits: practice and implementation

Delay computation in combinational logic circuits is complicated by the existence of unsensit-izable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but we use a recently developed single-vector condition, that is known to be necessary and suucient for a path to be responsible for the delay of a circuit (i.e. true) in the oating delay model. In this paper we build on this theory and develop an eecient and correct delay computation algorithm, for the oating mode delay. The algorithm uses a technique we call timed-test generation and can be incorporated into any stuck-at fault test generation framework. We describe in detail an implementation of the timed-test generation algorithm that uses both logical and timed, forward/backward implication and backtrace procedures to simultaneously prove the truth or falsity of sets of paths in the circuit. Logical and temporal connict detection during implication and backtrace are used to speed up the algorithm. Unlike previous techniques, the algorithm remains highly eecient even when a large number of distinct gate and path delays exist in the given circuit. We provide a comprehensive set of results that show signiicant speed-ups over previous delay computation techniques.